1. Field of the Invention
The present invention is related to a sampling front-end with capacitive digital to analog converter, and in particular, to a time-interleaved front-end for analog to digital converter.
2. Description of the Related Art
Low power consumption and high speed analog to digital converters (ADCs) are highly demanded for battery-powered mobile applications. For the application of high speed, the time-interleaved scheme is commonly used, which usually suffers from sampling mismatches between different channels. Furthermore, the capacitive DAC structure utilizes in the ADC also affect the speed of the conversion in each ADC channels. A good architecture of ADC front-end will facilitate the timing issue, and a well design capacitive DAC can enhance the conversion speed of each channel.